As semiconductor device geometries approach 0.25 .mu.m minimum feature size, increased attention has focused on the difficulty in fabricating reliable, high-performance, cost-effective, and manufacturable metallization stacks. The stacks have evolved from a simple single-layer aluminum alloy. Aluminum alloys remain the low-resistivity interconnect of choice; however, improvements in the multilayer scheme have led to aluminum alloy sandwiched between carefully chosen underlayers and overlayers. Underlayers such as Ti and Ti/TiN have been shown to increase the electrical performance of the interconnect (typical metric being electromigration resistance) by improving the grain structure (or crystallographic texture) of the Al (for reference, see for instance Rodbell et al. or Tracy et al.) and the grain size. In the unlikely event that a void should form in the Al metallization during testing or under operation, this underlayer also serves as a shunt layer and permits continuous current flow.
The overlayer has also evolved from a multilayer of Ti and Al or both, to containing a refractory such as TiN. The purpose of the overlayer is to reduce hillock formation and to behave as an antireflective coating (ARC) for lithography. In addition, since multilevel metallizations are commonplace and current must pass from one level of metallization to another through a plug (typically made of tungsten plus barrier metallization) and the overlayer, it must be comprised of sufficiently low resistance material.
As the dimensions of these vias or plugs reduce, the resistance of a typical circuit path is being dominated by the resistance of the plugs. Including more levels of plugs (driven by ever increasing number of metal layers) or reducing the dimensions of the metal interconnect lines leads to a higher resistance of the total connection. Therefore, it is important that the resistance of all layers in the current path be reduced.
It has recently been observed and published that highly-resistive Al-N forms between the Al and the TiN ARC. When a nitrogen plasma is struck above the Al-coated wafer during TiN reactive-sputtering, the formation energy of Al-N is lowered. This presence of Al-N was demonstrated by Inoue et al. using X-Ray Photoelectron Spectroscopy (XPS). It was also demonstrated in this work that the Al-N can be alleviated by the deposition of a Ti layer between the Al and the TiN in the metallization stack. This was shown to reduce the via resistance.
Furthermore, the inclusion of a Ti layer between the Al and the TiN improves the electromigration resistance. Also, the Ti under the TiN, which will react to form TiAl.sub.3, has served as an etch stop during subsequent processing.
The results of recent electromigration studies suggest that a leading candidate for the next generation metal stack is substrate/Ti/Al (or Al alloy)/Ti/TiN (FIG. 1). However, manufacturing such a metal stack using conventional processes presents some throughput problems. A typical deposition system for forming metal stacks has four physical vapor deposition chambers. Thus, using a conventional process (where a separate deposition chamber is used for each layer), all four chambers would be used to deposit the stack. FIG. 2 illustrates this conventional process. In step (i), a wafer (also referred to as a sample) 100 is moved into chamber 110 for underlayer (for example, Ti) deposition. In step (ii), wafer 100 is moved into chamber 120 for aluminum or aluminum alloy deposition. In step (iii), wafer 100 is moved into chamber 130 for Ti deposition, and in step (iv), wafer 100 is moved chamber 140 for TiN deposition. As a result, the system's throughput is limited because each wafer must be moved in and out of a chamber at least four times to form the underlayer/Al (or Al alloy)/Ti/TiN stack.
Additionally, because all four chambers are utilized for the metallization scheme, the flexibility of the system is greatly reduced.
Copending application "A PROCESS FOR IN-SITU DEPOSITION OF A Ti/TiN BARRIER METAL STACK", Ser. No. 08/347,781, filed on Nov. 30, 1994 by Paul R. Besser et al., discloses a process for IN-SITU deposition of a Ti/TiN barrier metal stack that avoids the throughput problems of the conventional processes described in conjunction with FIG. 2. Although the process disclosed in copending Application Ser. No. 08/347,781 is a great improvement over conventional processes, improvements in electrical characteristics, such as via resistance and electromigration performance are always desirable.